As computer systems evolve, so does the demand for increased memory for such systems. To increase memory density, some memory packages consist of several integrated circuit (IC) dies stacked one on top of the other. These stacked multi-die packages increase the capacity of each memory device without requiring additional space on the underlying circuit board or memory module. Furthermore, Thru-Silicon Via (TSV) technology is emerging as a popular solution for enabling the largest number of die-to-die interconnect in multi-die packages.
There are, however, a number of drawbacks associated with stacked multi-die packages, especially when TSV's are used as the interconnection means. For one, it is often desirable from a manufacturing cost perspective that all of the dies in the stack are derived from the same mask set, i.e., that all of the dies in a stack are substantially identical. When identical dies are stacked in a package and interconnected by TSV's, however, it is often difficult to selectively enable different modes of operation to a subset of the dies within the stack. For example, if the TSV's interconnect the stacked devices at the input/output (“IO”) pad of each die, there will be a large aggregation of capacitance at that point. In particular, each die contributes capacitance associated with that die's IO pad metal, IO device loading, IO devices, and electrostatic discharge (ESD) device loading. With such a large aggregated capacitance, the stack of die would become severely limited in operational speed compared to one of the die on its own.
In other stacked multi-die packages, the TSV's may interconnect the stacked dies internally, “behind” the IO system, using some sort of multi-drop data bus topology. In these packages, one of the dies acts as the “bus master”, while others act as “slave devices.” If the dies are substantially identical, it is difficult to designate one of the devices as the “bus master” without utilizing bus-multiplexing circuitry that is non-optimal from a cost and performance perspective.
In yet other stacked multi-die packages, it may be possible to add one or more manufacturing steps to modify some features or connections on some of the devices to facilitate die stacking. Performing such modifications, however, adds significant manufacturing and inventory control costs. As a result, the complexity and manufacturing and assembly costs for the stacked semiconductor device assembly are increased substantially.
As such it would be highly desirable to provide a stacked die assembly that utilizes substantially identical dies and that enables selective modes of operation for at least a subset of the dies in the stack.
Like reference numerals refer to the same or similar components throughout the several views of the drawings.